Step into Qinru Qiu’s lab at Binghamton University and you’ll see what appears to be a teenage boy’s fantasy: Rack after rack of sleek, black PlayStation 3 game systems.
And while she’s quick to explain that the PS3s are set up to emulate a multiprocessor, not for an epic showdown in Resident Evil, Qiu’s work may one day fuel new adolescent dreams. Her work on low-power computing could lead to smaller computers that function more efficiently and use less power.
The work holds such promise, in fact, that Qiu has received a grant from the National Science Foundation’s most prestigious program for young faculty. Her $409,000, five-year grant from the NSF’s Faculty Early Career Development (CAREER) Program will fund a project beginning in June. Less than a quarter of applicants received grants.
Qiu’s project focuses on reducing the power demands of multiprocessor system-on-chip designs, which are starting to become more popular. The PS3s, for instance, have one general purpose CPU and eight special synergistic processors.
A single processor can be very fast, but as its performance improves it requires more and more power. A multiprocessor, on the other hand, can deliver the same performance as numerous single processors at much lower power.
The benefits of cutting power demands include reduced energy consumption and lower manufacturing costs. Low-power designs can also improve reliability, since high power consumption increases the temperature of a chip, which harms its reliability.
Qiu, an assistant professor in the Department of Electrical and Computer Engineering, said her goal is to cut back the power demands of microprocessors while maintaining performance. Microprocessors are designed to deliver peak performance, even though users don’t need peak performance all the time.
“The basic idea is to slow the microprocessor down or put it into low-power mode when we’re not using it,” said Qiu, who believes the work has applications for everyday desktop machines as well as systems with high-end chips.
She traces her interest in low-power computing and dynamic power management back to her graduate studies. “Before, people just tried to minimize the power consumption of a chip when they designed it,” Qiu said. “Nowadays, more and more devices have many power modes, like a hard disk has a sleep mode, so we can have more control.”
For example, the industry uses the idea of a “time out.” After a certain amount of time, the computer goes into this mode to save power.
“A simple way to improve the ‘time out’ is to dynamically adjust the time-out period,” Qiu said. “If we know that whenever the computer gets idle it will be idle for a long time, the time-out period will be short. But if we know the user’s working style is working after a half-second of rest, then we can set the time period to be longer, because we don’t want it to turn on and turn off very frequently.”
Qiu investigates formal methods based on machine intelligence that learn the system workload and user behavior dynamically to enable such adaptive control. In addition to the user’s working style, adaptive power management takes into consideration the hardware, the software and the environment in which a system operates.
“We need something to detect the workload, predict the workload and characterize the hardware,” Qiu explained.
As part of the NSF project, Qiu will develop a new course on power management for senior-level undergraduates as well as graduate students. She is also teaching a system-on-chip class that was co-developed with local IBM engineers.
Qiu’s project will be the first systematic research for modeling, optimizing and evaluating adaptive and distributed power management for a large-scale multiprocessor system-on-chip design. And it comes at an opportune time, she said: Power demands have risen exponentially in the last couple of decades.
“In the 1990s, we were at 10 watts or 20 watts,” she said. “Nowadays a microprocessor can easily go up to 100 watts. And power density rises even faster because the chip gets smaller. With its current growing speed, the power density of a chip will soon exceed that of a nuclear reactor because of its size and consumption.”